Invention Grant
- Patent Title: Flip chip backside die grounding techniques
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Application No.: US16781720Application Date: 2020-02-04
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Publication No.: US11043467B2Publication Date: 2021-06-22
- Inventor: James Fred Salzman
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Rose Alyssa Keagy; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L23/373
- IPC: H01L23/373 ; H01L23/00 ; H01L27/118 ; H01L23/498 ; H01L23/31 ; H01L21/48 ; H01L23/552 ; H01L21/56

Abstract:
An integrated circuit is attached to a chip carrier in a flip chip configuration. An electrically conductive conformal layer is disposed on a back surface of the substrate of the integrated circuit. The electrically conductive conformal layer contacts the semiconductor material in the substrate and extending onto, and contacting, a substrate lead of the chip carrier. The substrate lead of the chip carrier is electrically coupled to a substrate bond pad of the integrated circuit. The substrate bond pad is electrically coupled through an interconnect region of the integrated circuit to the substrate of the integrated circuit. A component is attached to the chip carrier and covered with an electrically insulating material. The electrically conductive conformal layer also extends at least partially over the electrically insulating material on the component. The electrically conductive conformal layer is electrically isolated from the component by the electrically insulating material on the component.
Public/Granted literature
- US20200176413A1 Flip Chip Backside Die Grounding Techniques Public/Granted day:2020-06-04
Information query
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