Invention Grant
- Patent Title: Plate node configurations and operations for a memory array
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Application No.: US16666144Application Date: 2019-10-28
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Publication No.: US11043503B2Publication Date: 2021-06-22
- Inventor: Daniele Vimercati
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: H01L27/11514
- IPC: H01L27/11514 ; G11C11/22 ; H01L27/11507 ; G11C5/02

Abstract:
Methods, systems, and devices for plate node configurations and operations for a memory array are described. A single plate node of a memory array may be coupled to multiple rows or columns of memory cells (e.g., ferroelectric memory cells) in a deck of memory cells. The single plate node may perform the functions of multiple plate nodes. The number of contacts to couple the single plate node to the substrate may be less than the number of contacts to couple multiple plate nodes to the substrate. Connectors or sockets in a memory array with a single plate node may define a size that is less than a size of the connectors or sockets with multiple plate nodes. In some examples, a single plate node of the memory array may be coupled to multiple lines of a memory cells in multiple decks of memory cells.
Public/Granted literature
- US20200066737A1 PLATE NODE CONFIGURATIONS AND OPERATIONS FOR A MEMORY ARRAY Public/Granted day:2020-02-27
Information query
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