Invention Grant
- Patent Title: Vertical field effect transistor with low-resistance bottom source-drain contact
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Application No.: US16205344Application Date: 2018-11-30
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Publication No.: US11043598B2Publication Date: 2021-06-22
- Inventor: Choonghyun Lee , Soon-Cheon Seo , Injo Ok , Alexander Reznicek
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Michael A. Petrocelli
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L29/10 ; H01L21/324 ; H01L29/40 ; H01L29/417

Abstract:
A method of forming a semiconductor structure includes forming a metal liner above and in direct contact with a bottom source/drain region, a fin spacer on sidewalls of a fin extending upward from a substrate and a hard mask positioned on top of the fin, the bottom source/drain region includes an epitaxially grown material in direct contact with a bottom portion of the fin not covered by the fin spacer, forming an organic planarization layer directly above the metal liner, simultaneously etching the organic planarization layer and the metal liner until all portions of the metal liner perpendicular to the substrate have been removed and only portions of the metal liner parallel to the substrate remain in contact with the bottom source/drain region, and annealing the semiconductor structure to form a metal silicide layer from the portions of the metal liner in contact with the bottom source/drain region.
Public/Granted literature
- US20200176611A1 VERTICAL FIELD EFFECT TRANSISTOR WITH LOW-RESISTANCE BOTTOM SOURCE-DRAIN CONTACT Public/Granted day:2020-06-04
Information query
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