Invention Grant
- Patent Title: Variable delay circuits and methods
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Application No.: US15836093Application Date: 2017-12-08
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Publication No.: US11043942B2Publication Date: 2021-06-22
- Inventor: Chee Seng Leong
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Steven J. Cahill
- Main IPC: H03K5/159
- IPC: H03K5/159 ; H03K3/03 ; H03K5/131 ; H03K5/12 ; H03K5/00

Abstract:
A variable delay circuit includes first pull-up and first pull-down current paths and second pull-up and second pull-down current paths. The variable delay circuit generates first delays in an output signal relative to an input signal in response to the first pull-up and first pull-down current paths being enabled by a first control signal. The variable delay circuit generates second delays in the output signal relative to the input signal that are different than the first delays in response to the second pull-up and second pull-down current paths being enabled by a second control signal.
Public/Granted literature
- US20190123727A1 Variable Delay Circuits And Methods Public/Granted day:2019-04-25
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