A page buffer includes a bit line sensing circuit, a latch, and a main latch for sensing and storing data from a memory cell. The bit line sensing circuit is coupled with the memory cell by a bit line and configured to perform a bit line sensing operation of sensing first data stored in the memory cell. The latch control circuit is coupled with the bit line sensing circuit. The main latch is coupled with the bit line sensing circuit through the latch control circuit and configured to perform a main latch operation of storing the sensed first data. The cache latch is coupled with the main latch and configured to perform a cache latch operation of storing second data stored in the main latch. Wherein a period of time of the cache latch operation overlaps with a period of time of the bit line sensing operation.