A semiconductor memory device includes a first chip having a first pad and a first misalignment detection pattern on a first surface; and a second chip having a second pad and a second misalignment detection pattern on a second surface, and bonded to the first surface of the first chip such that the second pad is coupled with the first pad. The second chip includes a misalignment detection circuit which is coupled between the second misalignment detection pattern and a test pad and outputs a first voltage provided from the first misalignment detection pattern, to the test pad, in the case where a misalignment between the first chip and the second chip exceeds a preset value such that the first misalignment detection pattern and the second misalignment detection pattern are shorted to each other.