- Patent Title: Method for manufacturing a semiconductor structure comprising a semiconductor device layer formed on a tem, porary substrate having a graded SiGe etch stop layer therebetween
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Application No.: US15130182Application Date: 2016-04-15
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Publication No.: US11049797B2Publication Date: 2021-06-29
- Inventor: Yu-Hung Cheng , Shih-Pei Chou , Yeur-Luen Tu , Alexander Kalnitsky , Tung-I Lin , Wei-Li Chen
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee Address: TW Hsinchu
- Agency: WPAT, P.C., Intellectual Property Attorneys
- Agent Anthony King
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/48 ; H01L27/12 ; H01L21/306 ; H01L21/20 ; H01L21/762 ; H01L21/683
Abstract:
The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided.
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