Invention Grant
- Patent Title: Stacked type semiconductor memory device
-
Application No.: US15706559Application Date: 2017-09-15
-
Publication No.: US11049868B2Publication Date: 2021-06-29
- Inventor: Satoshi Nagashima , Tatsuya Kato , Wataru Sakamoto
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L27/11556 ; G11C16/04 ; G11C16/10 ; H01L29/788 ; H01L21/768 ; H01L23/528 ; H01L27/11521

Abstract:
A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other.
Public/Granted literature
- US20180006051A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2018-01-04
Information query
IPC分类: