Invention Grant
- Patent Title: NOR-type memory device and method of fabricating the same
-
Application No.: US16813035Application Date: 2020-03-09
-
Publication No.: US11049874B2Publication Date: 2021-06-29
- Inventor: Chen-Chih Wang , Li-Wei Ho
- Applicant: Chen-Chih Wang , Li-Wei Ho
- Applicant Address: TW Taipei; TW Taipei
- Assignee: Chen-Chih Wang,Li-Wei Ho
- Current Assignee: Chen-Chih Wang,Li-Wei Ho
- Current Assignee Address: TW Taipei; TW Taipei
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; H01L23/528 ; H01L27/11556 ; H01L23/522 ; H01L21/02 ; H01L21/762 ; H01L21/3213 ; H01L21/768 ; H01L27/11519 ; H01L27/11565 ; H01L21/28 ; G11C11/408 ; H01L27/108

Abstract:
The invention discloses a NOR-type memory device and a method of fabricating such NOR-type memory device. The NOR-type memory device according to a preferred embodiment of the invention includes a semiconductor substrate, a plurality of bit lines formed on the semiconductor substrate, a plurality of first isolation stripes, a plurality of second isolation stripes, a plurality of multi-layer stripes, a plurality of memory cells, a plurality of first sub-bit lines, a plurality of second sub-bit line, a plurality of word lines, an insulating layer, a plurality of grounded via contacts, and a grounding layer. The first isolation stripes and the second isolation stripes extend in a longitudinal direction defined by the semiconductor substrate. Each memory cell corresponds to one of the columns and one of the rows defined by the semiconductor substrate. The memory cells on one side of each first isolation stripe and the memory cells on the other side of said one first isolation stripe are staggeredly arranged. Each word line corresponds to one of the columns and connects the gate conductors of the memory cells along the corresponding column. The insulating layer is formed on the multi-layer stripes, the first isolation stripes and the second isolation stripes. Each of the grounded via contacts corresponds to one of the second sub-bit lines, and is formed through the insulating layer to connect the corresponding second sub-bit line. The grounding layer is formed on the insulating layer to connect all of the grounded via contacts.
Public/Granted literature
- US20200343260A1 NOR-TYPE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME Public/Granted day:2020-10-29
Information query
IPC分类: