Invention Grant
- Patent Title: Integrated circuit test apparatus and method
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Application No.: US16614395Application Date: 2018-05-17
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Publication No.: US11054469B2Publication Date: 2021-07-06
- Inventor: Michèle Portolan
- Applicant: INSTITUT POLYTECHNIQUE DE GRENOBLE
- Applicant Address: FR Grenoble
- Assignee: INSTITUT POLYTECHNIQUE DE GRENOBLE
- Current Assignee: INSTITUT POLYTECHNIQUE DE GRENOBLE
- Current Assignee Address: FR Grenoble
- Agency: Kenealy Vaidya LLP
- Priority: FR1754491 20170519
- International Application: PCT/FR2018/051182 WO 20180517
- International Announcement: WO2018/211218 WO 20181122
- Main IPC: G01R31/3177
- IPC: G01R31/3177 ; G06F21/72

Abstract:
Some embodiments are directed to a test apparatus for testing a device. The apparatus includes a test device having a memory for storing data processing instructions and processors configured, when the data processing instructions are executed, to execute test code in order to implement a test operation on the device being tested. The test code defines test patterns and test algorithms to be applied to instruments for testing the device being tested, and is in a first format that is independent of the test interface between the test device and the device being tested. The apparatus also includes an interface controller coupled to the device being tested and configured to convert communications generated by the test device during the execution of the test code into a second format suitable for the test interface, and to convert communications from the device being tested into the first format.
Public/Granted literature
- US20200150177A1 INTEGRATED CIRCUIT TEST APPARATUS AND METHOD Public/Granted day:2020-05-14
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