Invention Grant
- Patent Title: Error correction decoder and memory controller having the same
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Application No.: US16676320Application Date: 2019-11-06
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Publication No.: US11055164B2Publication Date: 2021-07-06
- Inventor: Soon Young Kang , Dae Sung Kim , Wan Je Sung , Myung Jin Jo , Jae Young Han
- Applicant: SK hynix Inc.
- Applicant Address: KR Icheon-si
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Icheon-si
- Agency: Perkins Coie LLP
- Priority: KR10-2019-0047439 20190423
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/07 ; G06F11/10 ; H03M13/11 ; H03M13/39 ; G06F13/16

Abstract:
There are provided an error correction decoder and a memory system having the same. The error correction decoder includes a node processor for performing at least one iteration of an error correction decoding based on at least one parameter used for an iterative decoding, a reliability information generator for generating reliability information corresponding to a current iteration upon a determination that the error correction decoding corresponding to the current iteration has been unsuccessful, and a parameter adjuster for adjusting the at least one parameter upon a determination that the reliability information satisfies a predetermined condition, and controlling the node processor to perform a next iteration based on the adjusted.
Public/Granted literature
- US20200341829A1 ERROR CORRECTION DECODER AND MEMORY CONTROLLER HAVING THE SAME Public/Granted day:2020-10-29
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