Error correction decoder and memory controller having the same
Abstract:
There are provided an error correction decoder and a memory system having the same. The error correction decoder includes a node processor for performing at least one iteration of an error correction decoding based on at least one parameter used for an iterative decoding, a reliability information generator for generating reliability information corresponding to a current iteration upon a determination that the error correction decoding corresponding to the current iteration has been unsuccessful, and a parameter adjuster for adjusting the at least one parameter upon a determination that the reliability information satisfies a predetermined condition, and controlling the node processor to perform a next iteration based on the adjusted.
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