Invention Grant
- Patent Title: Block level design method for heterogeneous PG-structure cells
-
Application No.: US16719481Application Date: 2019-12-18
-
Publication No.: US11055466B2Publication Date: 2021-07-06
- Inventor: Yen-Hung Lin , Yuan-Te Hou , Chung-Hsing Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: G06F30/30
- IPC: G06F30/30 ; G06F30/392 ; G06F30/39 ; G06F30/398 ; G06F119/06
Abstract:
A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.
Information query
