Flip flop circuit and data processing apparatus
Abstract:
Disclosed is a flip flop circuit including a master latch circuit receiving master input data based on target input data, a slave latch circuit configured to load master output data from the master latch circuit and to hold the master output data, and a data output section, target output data based on the target input data being output from the data output section. The slave latch circuit includes a first to an N-th slave latch circuits provided in parallel with the master latch circuit (N is an integer of 2 or larger), the flip flop circuit further includes an output selection circuit selecting any one of data output from the first to N-th slave latch circuits, and selection data from the output selection circuit is output from the data output section as the target output data.
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