Invention Grant
- Patent Title: Integrated circuit with physical layer interface circuit
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Application No.: US16879280Application Date: 2020-05-20
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Publication No.: US11057073B2Publication Date: 2021-07-06
- Inventor: Pascal Kamel Abouda , Alexis Nathanael Huot-Marchand , Matthieu Aribaud
- Applicant: NXP USA, Inc.
- Applicant Address: US TX Austin
- Assignee: NXP USA, Inc.
- Current Assignee: NXP USA, Inc.
- Current Assignee Address: US TX Austin
- Agent Rajeev Madnawat
- Priority: EP19305662 20190524
- Main IPC: H04B1/40
- IPC: H04B1/40 ; H03H7/38 ; H04B3/02

Abstract:
An integrated circuit for use in a differential network bus node comprising: a transceiver having a first transceiver input-output terminal and a second transceiver input-output terminal; a physical layer high terminal connected to the first transceiver input-output-terminal; a physical layer low terminal connected to the second transceiver input-output terminal; and a physical layer interface circuit comprising: a first low frequency RC matching circuit and a first high frequency RC matching circuit each connected between the first transceiver input-output-terminal and a first reference terminal; and a second low frequency RC matching circuit and a second high frequency RC matching circuit each connected between the second transceiver input-output terminal and a second reference terminal.
Public/Granted literature
- US20200373959A1 INTEGRATED CIRCUIT WITH PHYSICAL LAYER INTERFACE CIRCUIT Public/Granted day:2020-11-26
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