Invention Grant
- Patent Title: STT-MRAM failed address bypass circuit and STT-MRAM device including same
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Application No.: US16491648Application Date: 2018-03-16
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Publication No.: US11062788B2Publication Date: 2021-07-13
- Inventor: Sang-Gyu Park , Dong-Gi Lee
- Applicant: Industry-University Cooperation Foundation Hanyang University
- Applicant Address: KR Seoul
- Assignee: Industry-University Cooperation Foundation Hanyang University
- Current Assignee: Industry-University Cooperation Foundation Hanyang University
- Current Assignee Address: KR Seoul
- Agency: Sughrue Mion, PLLC
- Priority: KR10-2017-0033701 20170317
- International Application: PCT/KR2018/003067 WO 20180316
- International Announcement: WO2018/169335 WO 20180920
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C29/00 ; G11C11/16 ; G11C14/00 ; G11C29/44

Abstract:
A spin transfer torque magnetic random access memory (STT-MRAM) device according to the present embodiment comprises: an STT-MRAM memory array which includes a data storage unit for storing data, a defect area address storage unit for storing an address of a defect area, and a spare area for storing data of a failed area; and a bypass determination unit which includes a volatile information storage element for storing the address of the defect area, stored in the defect area address storage unit and provided thereto, and when memory array access occurs, compares an access address with the address of the defect area stored in the volatile information storage element and causes the memory array access to bypass to the spare area.
Public/Granted literature
- US20200013479A1 STT-MRAM FAILED ADDRESS BYPASS CIRCUIT AND STT-MRAM DEVICE INCLUDING SAME Public/Granted day:2020-01-09
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