STT-MRAM failed address bypass circuit and STT-MRAM device including same
Abstract:
A spin transfer torque magnetic random access memory (STT-MRAM) device according to the present embodiment comprises: an STT-MRAM memory array which includes a data storage unit for storing data, a defect area address storage unit for storing an address of a defect area, and a spare area for storing data of a failed area; and a bypass determination unit which includes a volatile information storage element for storing the address of the defect area, stored in the defect area address storage unit and provided thereto, and when memory array access occurs, compares an access address with the address of the defect area stored in the volatile information storage element and causes the memory array access to bypass to the spare area.
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