- Patent Title: Patterning process of a semiconductor structure with a middle layer
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Application No.: US16672705Application Date: 2019-11-04
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Publication No.: US11062905B2Publication Date: 2021-07-13
- Inventor: Chien-Chih Chen , Chien-Wei Wang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Hayne and Boone LLP
- Main IPC: G03F7/09
- IPC: G03F7/09 ; H01L21/033 ; H01L21/027

Abstract:
A lithography method is provided in accordance with some embodiments. The lithography method includes forming a metal-containing layer on a substrate, the metal-containing layer including a plurality of conjugates of metal-hydroxyl groups; treating the metal-containing layer at temperature that is lower than about 300° C. thereby causing a condensation reaction involving the plurality of conjugates of metal-hydroxyl groups; forming a patterned photosensitive layer on the treated metal-containing layer; and developing the patterned photosensitive layer so as to allow at least about 6% decrease of optimum exposure (Eop).
Public/Granted literature
- US20200066524A1 Patterning Process of a Semiconductor Structure with a Middle Layer Public/Granted day:2020-02-27
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