Invention Grant
- Patent Title: Structure and process of integrated circuit having latch-up suppression
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Application No.: US16521870Application Date: 2019-07-25
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Publication No.: US11062963B2Publication Date: 2021-07-13
- Inventor: Kuo-Hsiu Hsu , Yu-Kuan Lin , Feng-Ming Chang , Hsin-Wen Su , Lien Jung Hung , Ping-Wei Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L21/8238 ; H01L27/092 ; G11C11/412 ; H01L27/11 ; H01L21/762 ; G06F30/392

Abstract:
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side; a first fin active region extruded from the N-well of the semiconductor substrate; a second fin active region extruded from the P-well of the semiconductor substrate; a first isolation feature formed on the N-well and the P-well and laterally contacting the first and second fin active regions, the first isolation feature having a first width; and a second isolation feature inserted between the N-well and the P-well, the second isolation feature having a second width less than the first width.
Public/Granted literature
- US20200058564A1 Structure and Process of Integrated Circuit Having Latch-Up Suppression Public/Granted day:2020-02-20
Information query
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