Invention Grant
- Patent Title: Wafer level bump stack for chip scale package
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Application No.: US16588220Application Date: 2019-09-30
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Publication No.: US11064615B2Publication Date: 2021-07-13
- Inventor: Sreenivasan K Koduri
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Dawn Jos; Charles A. Brill; Frank D. Cimino
- Main IPC: H05K3/34
- IPC: H05K3/34 ; H05K1/02 ; H05K3/28 ; H05K3/38

Abstract:
A microelectronic device includes a die less than 300 microns thick, and an interface tile. Die attach leads on the interface tile are electrically coupled to die terminals on the die through interface bonds. The microelectronic device includes an interposer between the die and the interface tile. Lateral perimeters of the die, the interposer, and the interface tile are aligned with each other. The microelectronic device may be formed by forming the interface bonds and an interposer layer, while the die is part of a wafer and the interface tile is part of an interface lamina. Kerfs are formed through the interface lamina, through the interposer, and partway through the wafer, around a lateral perimeter of the die. Material is subsequently removed at a back surface of the die to the kerfs, so that a thickness of the die is less than 300 microns.
Public/Granted literature
- US20210100108A1 WAFER LEVEL BUMP STACK FOR CHIP SCALE PACKAGE Public/Granted day:2021-04-01
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