- Patent Title: Three-layer package-on-package structure and method forming same
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Application No.: US16723210Application Date: 2019-12-20
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Publication No.: US11069656B2Publication Date: 2021-07-20
- Inventor: Jui-Pin Hung , Feng-Cheng Hsu , Shin-Puu Jeng
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L25/065 ; H01L23/00 ; H01L21/56 ; H01L21/768 ; H01L21/3105 ; H01L25/00 ; H01L23/48 ; H01L23/31 ; H01L23/498 ; H01L21/48 ; H01L25/10 ; H01L23/538

Abstract:
A method includes forming a first plurality of redistribution lines, forming a first metal post over and electrically connected to the first plurality of redistribution lines, and bonding a first device die to the first plurality of redistribution lines. The first metal post and the first device die are encapsulated in a first encapsulating material. The first encapsulating material is then planarized. The method further includes forming a second metal post over and electrically connected to the first metal post, attaching a second device die to the first encapsulating material through an adhesive film, encapsulating the second metal post and the second device die in a second encapsulating material, planarizing the second encapsulating material, and forming a second plurality of redistributions over and electrically coupling to the second metal post and the second device die.
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