Invention Grant
- Patent Title: Device structure for a 3-dimensional NOR memory array and methods for improved erase operations applied thereto
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Application No.: US16509282Application Date: 2019-07-11
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Publication No.: US11069696B2Publication Date: 2021-07-20
- Inventor: Eli Harari , Raul Adrian Cernea , George Samachisa , Wu-Yi Henry Chien
- Applicant: Sunrise Memory Corporation
- Applicant Address: US CA Los Gatos
- Assignee: Sunrise Memory Corporation
- Current Assignee: Sunrise Memory Corporation
- Current Assignee Address: US CA Los Gatos
- Agency: VLP Law Group, LLP
- Agent Edward C. Kwok
- Main IPC: H01L27/112
- IPC: H01L27/112 ; H01L27/11556 ; H01L27/11582 ; G11C16/04 ; H01L27/12 ; G11C11/56 ; H01L27/06

Abstract:
A thin-film storage transistor includes (a) first and second polysilicon layers of a first conductivity serving, respectively, as a source terminal and a drain terminal of the thin-film storage transistor; (b) a third polysilicon layer of a second conductivity adjacent the first and second polysilicon layers, serving as a channel region of the thin-film storage transistor; (c) a conductor serving as a gate terminal of the thin-film storage transistor; and (d) a charge-trapping region between the conductor and third polysilicon layer, wherein a fourth body layer polysilicon of the second conductivity is included to provide an alternative source of free charge careers to accelerate device operation.
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