- Patent Title: DDR memory bus with a reduced data strobe signal preamble timespan
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Application No.: US16741368Application Date: 2020-01-13
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Publication No.: US11074959B2Publication Date: 2021-07-27
- Inventor: James A. McCall , Christopher P. Mozak , Christopher E. Cox , Yan Fu , Robert J. Friar , Hsien-Pao Yang
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: G11C11/40
- IPC: G11C11/40 ; G11C11/4072 ; G06F3/06 ; G11C7/10 ; G11C11/4093 ; G11C11/4076 ; G06F13/16

Abstract:
A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.
Public/Granted literature
- US20200286543A1 DDR MEMORY BUS WITH A REDUCED DATA STROBE SIGNAL PREAMBLE TIMESPAN Public/Granted day:2020-09-10
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