Invention Grant
- Patent Title: Vertically stacked transistors in a pin
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Application No.: US16475032Application Date: 2017-03-30
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Publication No.: US11075119B2Publication Date: 2021-07-27
- Inventor: Aaron D. Lilak , Sean T. Ma , Justin R. Weber , Patrick Morrow , Rishabh Mehandru
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP
- International Application: PCT/US2017/025004 WO 20170330
- International Announcement: WO2018/182615 WO 20181004
- Main IPC: H01L21/822
- IPC: H01L21/822 ; H01L21/02 ; H01L21/225 ; H01L21/265 ; H01L21/683 ; H01L21/762 ; H01L21/8234 ; H01L27/088 ; H01L29/167 ; H01L29/40 ; H01L29/66

Abstract:
An apparatus is provided which comprises: a fin; a layer formed on the fin, the layer dividing the fin in a first section and a second section; a first device formed on the first section of the fin; and a second device formed on the second section of the fin.
Public/Granted literature
- US20190326175A1 VERTICALLY STACKED TRANSISTORS IN A PIN Public/Granted day:2019-10-24
Information query
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