Invention Grant
- Patent Title: Underfill structure for semiconductor packages and methods of forming the same
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Application No.: US16177637Application Date: 2018-11-01
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Publication No.: US11075133B2Publication Date: 2021-07-27
- Inventor: Yu-Wei Chen , Li-Chung Kuo , Ying-Ching Shih , Szu-Wei Lu , Jing-Cheng Lin , Long Hua Lee , Kuan-Yu Huang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L23/498 ; H01L21/56 ; H01L23/00 ; H01L25/065

Abstract:
A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.
Public/Granted literature
- US20200006181A1 Underfill Structure for Semiconductor Packages and Methods of Forming the Same Public/Granted day:2020-01-02
Information query
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