Invention Grant
- Patent Title: Vertical NAND string multiple data line memory
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Application No.: US14810044Application Date: 2015-07-27
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Publication No.: US11075163B2Publication Date: 2021-07-27
- Inventor: Koji Sakui , Peter Sean Feeley , Akira Goda
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G11C16/04
- IPC: G11C16/04 ; H01L23/528 ; G11C11/56 ; H01L27/11529 ; H01L27/11556 ; H01L27/1157 ; H01L27/11582 ; H01L23/532 ; H01L23/535 ; H01L29/49
Abstract:
Apparatuses and methods are disclosed, including an apparatus with rows of vertical strings of memory cells coupled to a common source and multiple data lines associated with each row of vertical strings. Each data line associated with a row is coupled to at least one of the vertical strings in the row. Additional apparatuses and methods are described.
Public/Granted literature
- US20150333001A1 MULTIPLE DATA LINE MEMORY AND METHODS Public/Granted day:2015-11-19
Information query
