Invention Grant
- Patent Title: Filled through silicon vias for semiconductor packages and related methods
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Application No.: US15783239Application Date: 2017-10-13
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Publication No.: US11075306B2Publication Date: 2021-07-27
- Inventor: Bingzhi Su
- Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Applicant Address: US AZ Phoenix
- Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee Address: US AZ Phoenix
- Agency: Adam R. Stephenson, Ltd.
- Main IPC: H01L31/0203
- IPC: H01L31/0203 ; H01L27/146 ; H01L21/768

Abstract:
Implementations of semiconductor packages may include: a wafer having a first side and a second side, a solder pad coupled to the first side of the wafer, a through silicon via (TSV) extending from the second side of the wafer to the solder pad a metal layer around the walls of the TSV, and a low melting temperature solder in the TSV. The low melting temperature solder may also be coupled to the metal layer. The low melting temperature solder may couple to the solder pad through an opening in a base layer metal of the solder pad.
Public/Granted literature
- US20190115482A1 FILLED THROUGH SILICON VIAS FOR SEMICONDUCTOR PACKAGES AND RELATED METHODS Public/Granted day:2019-04-18
Information query
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