A storage device includes a nonvolatile memory and a controller. The controller is configured to control a first communication with a host device which is performed at a first transfer rate, and a second communication with the nonvolatile memory. The controller includes a detection circuit configured to detect a second transfer rate in the second communication with the nonvolatile memory, a processor configured to determine a target transfer rate in the first communication based on the second transfer rate detected by the detection circuit, and an interface configured to perform the first communication with the host device at the target transfer rate.