- Patent Title: Arithmetic processing apparatus and information processing system
-
Application No.: US16478292Application Date: 2017-12-14
-
Publication No.: US11080167B2Publication Date: 2021-08-03
- Inventor: Takahiro Okada , Tadaaki Yuba , Jun Ueshima , Shinichi Tsuchida , Ken Matsumoto
- Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
- Applicant Address: JP Kanagawa
- Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
- Current Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
- Current Assignee Address: JP Kanagawa
- Agency: Chip Law Group
- Priority: JPJP2017-011863 20170126
- International Application: PCT/JP2017/044910 WO 20171214
- International Announcement: WO2018/139097 WO 20180802
- Main IPC: G06F9/44
- IPC: G06F9/44 ; G06F11/36 ; G06F9/30 ; G06F9/38

Abstract:
A debug work is performed with respect to states after execution of a plurality of commands which is collectively issued from a processor to an arithmetic processing apparatus. A command register group holds commands issued from the processor in respective registers with a command chain including a plurality of commands as a unit. A command processing section processes the commands supplied from the command register group. A state machine manages processing states of the commands in the command processing section. A control section previously sets a condition under which stop is to be performed in the command chain as a stop condition and causes to stop the processing in the command processing section on the basis of the previously set stop condition and the processing states managed in the state machine.
Information query