Embodiments of the present disclosure relate to an apparatus comprising a memory and at least one processor. The at least one processor is configured to monitor one or more processing threads of a storage device. Each of the one or more processing threads includes two or more cache states. The at least one processor also updates one or more data structures to indicate a subject cache state of each of the one or more processing threads and detect an event that disrupts at least one of the one or more processing threads. Further, the processor determines a cache state of the at least one of the one or more processing threads contemporaneous to the disruption event using the one or more data structures and performs a recovery process for the disrupted at least one of the one or more processing threads.