Invention Grant
- Patent Title: Integrated circuit fin layout method, system, and structure
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Application No.: US16599552Application Date: 2019-10-11
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Publication No.: US11080453B2Publication Date: 2021-08-03
- Inventor: Po-Hsiang Huang , Sheng-Hsiung Chen , Chih-Hsin Ko , Fong-Yuan Chang , Clement Hsingjen Wann , Li-Chun Tien , Chia-Ming Hsu
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: G11C11/4076
- IPC: G11C11/4076 ; G11C11/4094 ; G11C7/10 ; G11C7/12 ; G11C7/18 ; G11C7/22 ; G06F30/392 ; H01L27/092 ; H01L29/66 ; H01L29/78 ; H01L21/8238 ; G06F30/367 ; G06F30/398 ; G06F30/3312 ; G06F111/20

Abstract:
A method of operating an IC manufacturing system includes determining whether an n-type active region of a cell or a p-type active region of the cell is a first active region based on a timing critical path of the cell, positioning the first active region along a cell height direction in an IC layout diagram of a cell, the first active region having a first total number of fins extending in a direction perpendicular to the cell height direction. The method also includes positioning a second active region in the cell along the cell height direction, the second active region being the n-type or p-type opposite the n-type or p-type of the first active region and having a second total number of fins less than the first total number of fins and extending in the direction, and storing the IC layout diagram of the cell in a cell library.
Information query
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