An image processing apparatus includes a processor configured to process an image; a reading direct memory access controller (DMAC) configured to read data from the memory; a writing DMAC configured to write data to the memory, each DMAC configured to control direct memory access to a memory; an upper first-in first-out (FIFO) unit connected to the reading and writing DMACs and includes FIFOs of the number equal to the number of channels of each of the reading and writing DMACs and a lower FIFO unit connected between the upper FIFO unit and the processor and includes FIFOs that correspond to the FIFOs of the upper FIFO unit at a ratio of 1 upper FIFO unit to F lower FIFO units (F being an integer equal to 2 or larger).