The present disclosure is related to a shift register unit. The shift register unit may include a shift register circuit and N output control circuits, wherein N is an integer larger than or equal to 2. The shift register circuit may be respectively electrically connected with an input signal terminal, a clock signal terminal, and an output node. Among the N output control circuits, an i-th output control circuit may be respectively electrically connected with an i-th control signal terminal of N control signal terminals, the output node, and an i-th gate line of N gate lines. i is a positive integer of smaller than or equal to N. The shift register unit may be configured to sequentially output a gate driving signal to the N gate lines respectively under control of the N control signal terminals.