A display device includes a signal controller configured to provide data and a frame control signal, a display panel including first to m-th data line groups, and a data driver configured to receive the data and the frame control signal, and output a data signal corresponding to the data to the first to m-th data line groups. The data driver includes first to m-th data driving circuit units electrically connected to the first to m-th data line groups in one-to-one correspondence, Each of the first to m-th data driving circuit units includes a clock adjustment unit configured to generate a second clock signal using a first clock signal and the frame control signal. The second clock signal controls an output timing of the data signal to be transmitted to a first channel among a plurality of channels of each of the first to m-th data line groups.