According to one embodiment, a memory system includes a semiconductor memory device including a first and second string each including cells coupled in series, and a memory controller configured to instruct the device to execute a write operation for writing data on any one of the cells in the first or second string. The first and second string are coupled in parallel between a bit line and a source line, and coupled to different word lines. The write operation includes a first write operation and a second write operation executed after the first write operation. The controller is configured to instruct the device to execute a first write operation on a second cell in the second string between a first write operation on a first cell in the first string and a second write operation on the first cell.