Invention Grant
- Patent Title: Memory plane structure for ultra-low read latency applications in non-volatile memories
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Application No.: US16668949Application Date: 2019-10-30
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Publication No.: US11081192B2Publication Date: 2021-08-03
- Inventor: Hiroki Yabe , Koichiro Hayashi , Takuya Ariki , Yuki Fujita , Naoki Ookuma , Kazuki Yamauchi , Masahito Takehara , Toru Miwa
- Applicant: SanDisk Technologies LLC
- Applicant Address: US TX Addison
- Assignee: SanDisk Technologies LLC
- Current Assignee: SanDisk Technologies LLC
- Current Assignee Address: US TX Addison
- Agency: Dickinson Wright PLLC
- Agent Steven Hurles
- Main IPC: G11C16/32
- IPC: G11C16/32 ; G11C16/26

Abstract:
A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.
Public/Granted literature
- US20210134375A1 MEMORY PLANE STRUCTURE FOR ULTRA-LOW READ LATENCY APPLICATIONS IN NON-VOLATILE MEMORIES Public/Granted day:2021-05-06
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