Invention Grant
- Patent Title: Chip package process
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Application No.: US15636646Application Date: 2017-06-29
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Publication No.: US11081371B2Publication Date: 2021-08-03
- Inventor: Wen-Yuan Chang , Wei-Cheng Chen , Hsueh-Chung Shelton Lu
- Applicant: VIA Alliance Semiconductor Co., Ltd.
- Applicant Address: CN Shanghai
- Assignee: VIA Alliance Semiconductor Co., Ltd.
- Current Assignee: VIA Alliance Semiconductor Co., Ltd.
- Current Assignee Address: CN Shanghai
- Agency: JCIPRNET
- Priority: TW106115540 20170511
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L23/00 ; H01L21/78 ; H01L23/31
Abstract:
A chip package process includes the following steps. A supporting structure and a carrier plate are provided. The supporting structure has a plurality of openings. The supporting structure is disposed on the carrier plate. A plurality of chips is disposed on the carrier plate. The chips are respectively located in the openings of the supporting structure. An encapsulated material is formed to cover the supporting structure and the chips. The supporting structure and the chips are located between the encapsulated material and the carrier plate. The encapsulated material is filled between the openings and the chips. The carrier plate is removed. A redistribution structure is disposed on the supporting structure, wherein the redistribution structure is connected to the chips.
Public/Granted literature
- US20180061672A1 CHIP PACKAGE PROCESS Public/Granted day:2018-03-01
Information query
IPC分类:
