A semiconductor device that includes active patterns defined in a substrate, and gate patterns extending in a first direction while traversing the active patterns. First wiring line patterns disposed over a first dielectric layer which covers the gate patterns, and extending in the first direction. The first wiring line patterns comprise internal wiring line patterns coupled with first vertical vias, which pass through the first dielectric layer and are coupled to the active patterns and the gate patterns, and power routing patterns not coupled with the first vertical vias. The first wiring line patterns are aligned in conformity with virtual wiring line pattern tracks which are defined at a first pitch along a second direction intersecting with the first direction, and the first active patterns are disposed between the power routing patterns when viewed on a top.