Invention Grant
- Patent Title: Semiconductor package and methods of manufacturing a semiconductor package
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Application No.: US16282420Application Date: 2019-02-22
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Publication No.: US11081457B2Publication Date: 2021-08-03
- Inventor: Thomas Feil , Danny Clavette , Paul Ganitzer , Martin Poelzl , Carsten von Koblinski
- Applicant: Infineon Technologies Austria AG
- Applicant Address: AT Villach
- Assignee: Infineon Technologies Austria AG
- Current Assignee: Infineon Technologies Austria AG
- Current Assignee Address: AT Villach
- Agency: Murphy, Bilak & Homilier, PLLC
- Priority: EP18158473 20180223
- Main IPC: H01L25/16
- IPC: H01L25/16 ; H01L23/31 ; H01L23/538 ; H01L21/48 ; H01L21/56 ; H01L23/00 ; H01L21/78 ; H01L23/29 ; H01L25/07 ; H01L21/683 ; H01L27/088

Abstract:
In an embodiment, a semiconductor package includes a first transistor device having first and second opposing surfaces, a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface. A first metallization structure arranged on the first surface includes a plurality of outer contact pads which includes a protective layer of solder, Ag or Sn. A second metallization structure is arranged on the second surface. A conductive connection extending from the first surface to the second surface electrically connects the second power electrode to an outer contact pad of the first metallization structure. A first epoxy layer arranged on side faces and on the first surface of the transistor device includes openings which define a lateral size of the plurality of outer contact pads and a package footprint.
Public/Granted literature
- US20190267362A1 Semiconductor Package and Methods of Manufacturing a Semiconductor Package Public/Granted day:2019-08-29
Information query
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