Invention Grant
- Patent Title: Method of manufacturing semiconductor devices using a capping layer in forming gate electrode and semiconductor devices
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Application No.: US16532274Application Date: 2019-08-05
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Publication No.: US11081584B2Publication Date: 2021-08-03
- Inventor: Chandrashekhar Prakash Savant , Kin Shun Chong , Tien-Wei Yu , Chia-Ming Tsai , Ming-Te Chen
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McDermott Will & Emery LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L21/02
Abstract:
In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.
Information query
IPC分类:
