A duty cycle correction circuit includes: a first inverter, a first delayer, and a first adjustment circuit. An input terminal and output terminal of the first inverter are respectively configured to receive a first signal and output a third signal. A first input terminal and an output terminal of the first adjustment circuit are respectively configured to receive the third signal and output a first correction signal. An input terminal and output terminal of the first delayer are respectively configured to input a second signal and output a fourth signal to the first adjustment circuit. The fourth signal has a first delay time relative to the second signal. When the third signal and the fourth signal are at a high level, so is the first correction signal. When the third signal and the fourth signal are at a low level, so is the first correction signal.