Invention Grant
- Patent Title: Method of manufacturing semiconductor elements
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Application No.: US16802782Application Date: 2020-02-27
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Publication No.: US11094536B2Publication Date: 2021-08-17
- Inventor: Haruhiko Nishikage , Yoshinori Miyamoto , Yasunobu Hosokawa
- Applicant: NICHIA CORPORATION
- Applicant Address: JP Anan
- Assignee: NICHIA CORPORATION
- Current Assignee: NICHIA CORPORATION
- Current Assignee Address: JP Anan
- Agency: Foley & Lardner LLP
- Priority: JPJP2019-036768 20190228,JPJP2020-016939 20200204
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/78 ; H01L29/20

Abstract:
A method of manufacturing semiconductor elements includes: disposing a semiconductor layer made of a nitride semiconductor on a first wafer; and bonding a second wafer to the first wafer via the semiconductor layer. The first wafer has an upper surface including a first region and a second region surrounding a periphery of the first region and located lower than the first region. In a top view of the first wafer, a first distance between an edge of the first wafer and the first region of the first wafer in each of a plurality of first directions parallel to respective m-axes of the semiconductor layer is smaller than a second distance between the edge of the first wafer and the first region of the first wafer in each of a plurality of second directions parallel to respective a-axes of the semiconductor layer.
Public/Granted literature
- US20200279730A1 METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENTS Public/Granted day:2020-09-03
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