Invention Grant
- Patent Title: Simultaneous bonding approach for high quality wafer stacking applications
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Application No.: US16429145Application Date: 2019-06-03
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Publication No.: US11094575B2Publication Date: 2021-08-17
- Inventor: Xin-Hua Huang , Ping-Yin Liu , Chang-Chen Tsao
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L21/68
- IPC: H01L21/68 ; H01L21/683 ; H01L21/18 ; H01L21/687

Abstract:
In some embodiments, the present disclosure relates to a method for bonding a first wafer to a second wafer. The method includes aligning a first wafer with a second wafer, so the first and second wafers are vertically stacked and have substantially planar profiles extending laterally in parallel. The method further includes bringing the first and second wafers into direct contact with each other at an inter-wafer interface. The bringing of the first and second wafers into direct contact includes deforming the first wafer so that the first wafer has a curved profile and that the inter-wafer interface is localized to a center of the first wafer. The second wafer maintains its substantially planar profile throughout the deforming of the first wafer. The method further includes deforming the first wafer and/or the second wafer to gradually expand the inter-wafer interface from the center to an edge of the first wafer.
Public/Granted literature
- US20200381283A1 SIMULTANEOUS BONDING APPROACH FOR HIGH QUALITY WAFER STACKING APPLICATIONS Public/Granted day:2020-12-03
Information query
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