Invention Grant
- Patent Title: Hybrid architectures for check node processing of extended min-sum (EMS) decoding of non-binary LDPC codes
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Application No.: US16621956Application Date: 2018-06-07
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Publication No.: US11095308B2Publication Date: 2021-08-17
- Inventor: Cédric Marchand , Emmanuel Boutillon
- Applicant: UNIVERSITE DE BRETAGNE SUD
- Applicant Address: FR Lorient
- Assignee: UNIVERSITE DE BRETAGNE SUD
- Current Assignee: UNIVERSITE DE BRETAGNE SUD
- Current Assignee Address: FR Lorient
- Agency: Meagher Emanuel Laks Goldberg & Liao, LLP
- Priority: EP17305747 20170619
- International Application: PCT/EP2018/064995 WO 20180607
- International Announcement: WO2018/234053 WO 20181227
- Main IPC: H03M13/11
- IPC: H03M13/11

Abstract:
A check node processing unit configured to determine check node messages to decode a signal encoded using NB-LDPC code, the check node processing unit comprising: a data link to one or more message presorting units configured to determine permuted variable node messages by permuting variable node messages generated by one or more variable node processing units; a syndrome sub-check node configured to determine check node messages from a set of syndromes, the set of syndromes being determined from one or more intermediate messages computed from the permuted variable node messages; a forward-backward sub-check node configured to determine permuted check node messages from the intermediate messages; a switching unit configured to generate check node messages of given index from the check node messages or from the permuted check node messages depending on the giving index.
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Information query
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