To improve a timing error detection accuracy in a semiconductor integrated circuit provided with storage devices operating in synchronization with a clock signal.
A delay part delays a data signal by two mutually-different delay times and outputs it as first and second delay signals. A holding part holds the first and second delay signals in synchronization with a timing signal for giving an instruction on a predetermined capture timing. A setup time detection part detects whether or not one of the first and second delay signals held within a setup-time detection period from a predetermined start timing to the predetermined capture timing has changed. A hold time detection part detects whether or not the other of the first and second delay signals held within a hold-time detection period from the predetermined capture timing to a predetermined end timing has changed.