Embodiments presented herein provide techniques for planning and scheduling a semiconductor back end factory. The technique begins by running a first mathematical programing model applied to factory data and production targets that produces a solution and processing the solution to produce a bottleneck loading plan for at least one machine of the factory's bottleneck machine families. The technique further includes running a second mathematical programing model applied to the bottleneck loading plan that produces a solution and processing the solution to produce a conversion schedule for the at least one machine of the bottleneck machine families. The technique further includes creating a lot schedule for the factory by running a simulation that follows the conversion schedule. The technique further includes publishing the lot schedule.