Invention Grant
- Patent Title: Semiconductor integrated circuit device
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Application No.: US16684322Application Date: 2019-11-14
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Publication No.: US11101292B2Publication Date: 2021-08-24
- Inventor: Isaya Sobue
- Applicant: SOCIONEXT INC.
- Applicant Address: JP Kanagawa
- Assignee: SOCIONEXT INC.
- Current Assignee: SOCIONEXT INC.
- Current Assignee Address: JP Kanagawa
- Agency: McDermott Will and Emery LLP
- Priority: JPJP2017-096404 20170515
- Main IPC: H01L27/118
- IPC: H01L27/118 ; H01L27/02

Abstract:
A semiconductor integrated circuit device including a plurality of rows of IO cells has a configuration capable of avoiding a latchup error without causing an increase in area. The device includes a first IO cell row placed closest to an edge of a chip and a second IO cell row placed adjacent to a core region side of the first IO cell row. Each of the IO cells of the first and second IO cell rows has a high power supply voltage region and a low power supply voltage region provided separately in a direction perpendicular to a direction in which the IO cells are lined up. The IO cell rows are placed so that the high power supply voltage regions of these rows are mutually opposed.
Public/Granted literature
- US20200083252A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2020-03-12
Information query
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