A frequency multiplier, a digital phase-locked loop circuit, and a frequency multiplication method, where the frequency multiplier includes a clock controller configured to: receive an output signal from a time-to-digital converter in the digital phase-locked loop circuit, and generate a control signal based on a duty cycle error of the output signal, a clock calibration circuit configured to: receive a reference clock signal, calibrate a duty cycle of the reference clock signal based on the control signal, and output a calibrated clock signal, and a clock frequency multiplier configured to: receive the calibrated clock signal, multiply a frequency of the calibrated clock signal, and output a frequency multiplied signal to the time-to-digital converter.