An circuit includes: a plurality of analog-to-digital converters (ADCs) and a control chip. The control chip is utilized for instructing a target ADC to output audio data of a target channel during a target period, and utilized for instructing remaining ADCs not to output audio data in the target period. Then, the control chip defines data timing of the target channel and other channels based on the data receiving time point of the audio data of the target channel. The plurality of ADCs would process analog audio signals of a plurality of channels and output audio data of the plurality of channels according to an assigned order configured by the control chip to form a serial data signal. The control chip separates the audio data of different channels from the serial data signal according to the data timing of the plurality of channels.