Program source code defined in a multi-threaded imperative programming language can be compiled into a circuit description for a synchronous digital circuit (“SDC”) that includes pipelines and queues. During compilation, data defining a debugging network for the SDC can be added to the circuit description. The circuit description can then be used to generate the SDC such as, for instance, on an FPGA. A CPU connected to the SDC can utilize the debugging network to query the pipelines for state information such as, for instance, data indicating that an input queue for a pipeline is empty, data indicating the state of an output queue, or data indicating if a wait condition for a pipeline has been satisfied. A profiling tool can execute on the CPU for use in debugging the SDC.