Invention Grant
- Patent Title: Methods and apparatus for reducing reliability degradation on an integrated circuit
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Application No.: US15718685Application Date: 2017-09-28
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Publication No.: US11113442B2Publication Date: 2021-09-07
- Inventor: Ning Cheng , Xiangyong Wang , Mahesh A. Iyer
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F30/00
- IPC: G06F30/00 ; G06F30/392 ; G06F30/34 ; G06F30/394 ; G06F30/398 ; G06F119/04

Abstract:
An integrated circuit with programmable logic circuitry is provided. The integrated circuit may include quiet regions, toggling regions, or unused regions. An integrated circuit may also include heavily-used metal routing paths, lightly-used metal routing paths, and unused metal routing paths. Circuit design tools may be used to generate multiple configuration images that replace the quiet regions with toggling or unused regions, that swap the heavily-used metal routing paths with lightly-used or unused metal routing paths, or that use random fitter seeds of improve the usage coverage to statistically reduce the always quiet regions on the integrated circuit. The multiple configuration images implement the same design and can be used to reconfigure the integrated circuit upon startup to reduce aging effects and improve circuit performance.
Public/Granted literature
- US20190095571A1 METHODS AND APPARATUS FOR REDUCING RELIABILITY DEGRADATION ON AN INTEGRATED CIRCUIT Public/Granted day:2019-03-28
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