Invention Grant
- Patent Title: Three-dimensional nor array including vertical word lines and discrete channels and methods of making the same
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Application No.: US16728825Application Date: 2019-12-27
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Publication No.: US11114534B2Publication Date: 2021-09-07
- Inventor: Adarsh Rajashekhar , Fei Zhou , Raghuveer S. Makala , Yanli Zhang , Rahul Sharangpani
- Applicant: SANDISK TECHNOLOGIES LLC
- Applicant Address: US TX Addison
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Addison
- Agency: The Marbury Law Group PLLC
- Main IPC: H01L29/417
- IPC: H01L29/417 ; H01L27/11597 ; H01L27/11582 ; H01L27/11556

Abstract:
A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, memory openings vertically extending through the alternating stack, vertical word lines located in each one of the memory openings and vertically extending through each of the source layers and the drain layers of the alternating stack, vertical stacks of discrete semiconductor channels located in each one of the memory openings and contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source layers and a drain layer of the drain layers, and vertical stacks of discrete memory material portions located in each one of the memory openings and laterally surrounding a respective one of the vertical word lines. Each memory material portion is laterally spaced from a respective one of the semiconductor channels by a respective gate dielectric layer.
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